In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. INTRODUCTION. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become increasingly stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental varia-tions. An analytical comparison of three different receiver architectures, including transimpedance, integrating, and totem-pole diode pair, is. We have proposed latency-optimized MFS with serial optical interface with two different inter-chip communication strategies. The crosstalk has major concern on VLSI technology because it totally changes the system performance.
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